Flip Chip Ball Grid Array (FCBGA) package with large silicon chip and package size typically exhibits high warpage and coplanarity. Many percieved that such package design faced surface mount technology (SMT) challenges. In this study, the warpage characteristic and the SMT validation for such large package was investigated. A hybrid methodology utilizing both numerical and empirical data to predict the coplanarity of this package is presented. SMT validation was performed on range of coplanarity to demonstrate the process robustness together with solder joint reliability (SJR) data. With all the studies, the correlation between package room temperature coplanarity and reflow warpage has been established without comprising SMT quality and SJR performance. In the end, an improved FCBGA coplanarity specification limit has been defined and aligned with the Alternate Warpage Specification in JEDEC standard.
