The negative bias temperature instability (NBTI) of nanoscaled Si"0"."4"5Ge"0"."5"5 pFETs with different thicknesses of the Si passivation layer (cap) is studied. Individual discharge events are detected in the measured threshold voltage shift (@DV"t"h) relaxation traces, with exponentially distributed step heights. The use of a thinner Si cap is shown to reduce both the average number of charge/discharge events and the average @DV"t"h step height. To qualitatively explain the experimental observations, a simple model including a defect band in the dielectric is proposed.
