CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks
| العنوان: | CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks |
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| المؤلفون: | Saunak Saha, Joseph Zambreno, Henry Duwe |
| المصدر: | Journal of Signal Processing Systems. 92:907-929 |
| بيانات النشر: | Springer Science and Business Media LLC, 2020. |
| سنة النشر: | 2020 |
| مصطلحات موضوعية: | Spiking neural network, Adaptive memory, Artificial neural network, Computer science, Distributed computing, 020206 networking & telecommunications, 02 engineering and technology, Energy consumption, Theoretical Computer Science, Memory management, Hardware and Architecture, Control and Systems Engineering, Modeling and Simulation, Signal Processing, Dynamic demand, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Enhanced Data Rates for GSM Evolution, Information Systems, Efficient energy use |
| الوصف: | While neural network models keep scaling in depth and computational requirements, biologically accurate models are becoming more interesting for low-cost inference. Coupled with the need to bring more computation to the edge in resource-constrained embedded and IoT devices, specialized ultra-low power accelerators for spiking neural networks are being developed. Having a large variance in the models employed in these networks, these accelerators need to be flexible, user-configurable, performant and energy efficient. In this paper, we describe CyNAPSE, a fully digital accelerator designed to emulate neural dynamics of diverse spiking networks. Since the use case of our implementation is primarily concerned with energy efficiency, we take a closer look at the factors that could improve its energy consumption. We observe that while majority of its dynamic power consumption can be credited to memory traffic, its on-chip components suffer greatly from static leakage. Given that the event-driven spike processing algorithm is naturally memory-intensive and has a large number of idle processing elements, it makes sense to tackle each of these problems towards a more efficient hardware implementation. With a diverse set of network benchmarks, we incorporate a detailed study of memory patterns that ultimately informs our choice of an application-specific network-adaptive memory management strategy to reduce dynamic power consumption of the chip. Subsequently, we also propose and evaluate a leakage mitigation strategy for runtime control of idle power. Using both the RTL implementation and a software simulation of CyNAPSE, we measure the relative benefits of these undertakings. Results show that our adaptive memory management policy results in up to 22% more reduction in dynamic power consumption compared to conventional policies. The runtime leakage mitigation techniques show that up to 99.92% and at least 14% savings in leakage energy consumption is achievable in CyNAPSE hardware modules. |
| تدمد: | 1939-8115 1939-8018 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::bc8c80ba054fead5399fa8bcfca14560 https://doi.org/10.1007/s11265-020-01546-x |
| حقوق: | CLOSED |
| رقم الأكسشن: | edsair.doi...........bc8c80ba054fead5399fa8bcfca14560 |
| قاعدة البيانات: | OpenAIRE |
Find this article in full text from Springer Verlag. | تدمد: | 19398115 19398018 |
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