With the continuous shrinking of feature dimensions towards sub-28nm regime in the semiconductor industry, the traditional design rules can longer satisfy the communication needs between the physical designer and the manufacturer. Thus, one may possibly encounter novel yield killers even if all the DRC rules have passed. To address such challenges in the design space, a virtual FAB range pattern matching (RPM) flow is proposed to explore the design space. The Design Generator is used to make design-like layouts without any design rule violation. Virtual lithography simulation is then used to find potential problematic hotspots. These hotspots will make up the pattern library for certain processes. When real designs come in, range pattern matching will be performed on the target layout and find out suspected hotspots. Special treatment will be placed on these potential process killers.
