The High Definition X-ray Imager (HDXI) for the proposed Lynx X-ray Observatory will require much larger (16 Mpixel) and faster (around 100 fps) imaging detectors than have been developed to date. One engineering solution to meet these requirements is to combine substantial parallelization with fast readout speeds. Stanford University and MIT are collaborating in the development of such detectors. The work involves the design of a new ASIC, the MIT CCD Readout Chip MCRC-V1, developed to read out MIT Lincoln Laboratory CCDs using MOSFET or JFET outputs. The architecture of the MCRC-V1 involves eight low-noise, fully differential amplifiers, each coupled to a fully differential output driver to support waveform sampling with a commercial ADC. The chip also includes an experimental current readout capability to support fixed-bias potential operation of single-electron sensitive readout (SiSeRo) CCD output stages. We will present both the readout concept and circuit details for the MCRC-V1 ASIC.
