As SRAM integration scheme becomes more and more aggressive in term of development time, supply voltage and geometric dimension, parameter extraction techniques need to be continuously upgraded to ensure the best support for technology development. An innovative approach for write-margin extraction has recently been published at the ISSCC'2006 conference. This approach makes use of test structure giving access to internal node. Here, this approach is evaluated through our 65 nm process and it is shown that the layout and probing of the innovative test structure induces a write delay. As a consequence an adaptation of this innovative methodology is proposed. The new combined solution gives promising results, in terms of accuracy and spread, to better follow the process development of advanced SRAM.
