Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability
التفاصيل البيبلوغرافية
العنوان:
Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability
This paper shows high-pressure anneal (HPA) as a performance booster for Si-passivated strained Ge (sGe) p-channel FinFET and gate-all-around (GAA) devices. Improved interface quality and hole mobility (∼600 cm2/Vs) are obtained on FinFET after HPA at 450°C. While V th is tuned by ∼400 mV using TiAl work function metal (WFM), HPA-induced increases in J g and NBTI are suppressed by barrier layer engineering under the TiAl. Finally, the optimized HPA is also shown to improve the electrostatics and overall performance of GAA devices, reaching SS lin of 65 mV/dec at L g =60 nm and a Q factor of 15 with low I off of ∼3×10−9 A/μm.
