A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell
| العنوان: | A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell |
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| المؤلفون: | T. Ozaki, Daisaburo Takashima, Yasushi Nagadomi |
| المصدر: | IEEE Journal of Solid-State Circuits. 46:681-689 |
| بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE), 2011. |
| سنة النشر: | 2011 |
| مصطلحات موضوعية: | Engineering, Sense amplifier, business.industry, Transistor, Electrical engineering, Integrated circuit design, Capacitance, Ferroelectric capacitor, law.invention, Non-volatile memory, Capacitor, law, Ferroelectric RAM, Electronic engineering, Electrical and Electronic Engineering, business |
| الوصف: | This paper proposes a new ladder FeRAM ar chitecture with capacitance-coupled-bitline (CCB) cells for high-end embedded applications. The ladder FeRAM architecture short-circuits both electrodes of each ferroelectric capacitor at every standby cycle. This overcomes the fatal disturbance problem inherent to the CCB cell, and halves read/write cycle time by sharing a plateline and its driver with 32 cells in two neighboring ladder blocks. This configuration realizes small 0.35 μm2 cell using a highly reliable ferroelectric capacitor of as large as 0.145 μm2 size, and a highly compatible process with logic-LSI. A slow plateline drive of the CCB cell due to a resistive plateline using an active area is minimized to 2.5 ns by introducing thick M3 shunt-path and distributed M3 platelines. The area penalty of the shunt is 4.7% of an array. A serious bitline-to-bitline coupling noise in edge bitlines up to the noise/signal ratio of 0.38 due to the operation peculiar to FeRAM is eliminated by introducing activated dummy bitlines and their sense amplifiers. The design of 16 cells in a ladder block is optimal for effective cell size, cell signal, and active power dissipation. A new early plateline pull-down read scheme omits "0"-data rewrite operation without read disturbance. A 64 Kb ladder FeRAM with the CCB cells and the early plateline pull-down read scheme achieves a fast random read/write of 10 ns cycle and 8 ns access at 150°C. |
| تدمد: | 1558-173X 0018-9200 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::d2e0535132213db438dac8746a200a16 https://doi.org/10.1109/jssc.2010.2098210 |
| حقوق: | CLOSED |
| رقم الأكسشن: | edsair.doi...........d2e0535132213db438dac8746a200a16 |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 1558173X 00189200 |
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