High performance dual-gate ISFET with non-ideal effect reduction schemes in a SOI-CMOS bioelectrical SoC

التفاصيل البيبلوغرافية
العنوان: High performance dual-gate ISFET with non-ideal effect reduction schemes in a SOI-CMOS bioelectrical SoC
المؤلفون: L.-S. Jeng, Yi-Shao Liu, Ming-Jer Chen, Yang Jing-Hwang, C. K. Yang, Tsui Felix Ying-Kit, Yi-Chun Huang, Tung-Tsun Chen, Jui-Cheng Huang, Chin-Hua Wen, C. H. Hsieh, C.-C. Lin, Sheng-Da Liu
المصدر: 2015 IEEE International Electron Devices Meeting (IEDM).
بيانات النشر: IEEE, 2015.
سنة النشر: 2015
مصطلحات موضوعية: Hysteresis, Materials science, Signal-to-noise ratio (imaging), CMOS, law, Logic gate, Transistor, Electronic engineering, Biasing, ISFET, Sensitivity (electronics), law.invention
الوصف: A dual-gate ion-sensitive field-effect transistor (DGFET) with the back-side sensing structure implemented in a 0.18 μm SOI-CMOS SoC platform realizing high performance bioelectrical detection with non-ideal effect reduction is presented. Non-ideal effects of the conventional ISFET, such as time drift and hysteresis, are suppressed by the innovative scheme in DGFET using the bottom poly-gate (PG) transistor instead of the fluidic gate (FG) transistor for sensing. As a result, the signal-to-noise ratio (SNR) is improved by 155x, time drift is reduced by 53x, and hysteresis is reduced by 3.7x. For certain applications which require high sensitivity, a pulse-modulated biasing technique can be adopted to effectively reduce time drift with high pH sensitivity of 453 mV/pH which is ∼7.5x enhancement over the Nernst limit in the proposed DGFET.
URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::d74a1c3577c92fce4e22962e46fbc797
https://doi.org/10.1109/iedm.2015.7409792
رقم الأكسشن: edsair.doi...........d74a1c3577c92fce4e22962e46fbc797
قاعدة البيانات: OpenAIRE