The 700mm2 65nm Itanium® processor codenamed Tukwila [1] integrates four cores and a system interface with six QuickPath® interconnect channels and four memory interconnect channels. The large die, shown in Fig. 3.4.6, and high level of integration coupled with process variability present clock-system design challenges in the areas of power consumption and variability compensation that we discuss in this paper. Figure 3.4.1 shows the clock system, which is a cascaded-PLL architecture with an initial filter PLL that receives a 133MHz reference clock. This maiden PLL filters reference-clock jitter and outputs a 133MHz clock to 13 downstream PLLs. Each downstream PLL has a duty-cycle corrector that monitors and corrects the end-of-route duty cycle.
