Systematic defects have drawn a lot of focus from the semiconductor industry, especially in the technology development and early technology ramp. However, random defects are still dominant when the technology is mature and in highvolume manufacturing. Historically, foundries have run critical area analysis on incoming designs in order to identify the yield-limiting failure modes and estimate the yield loss. However, with growing design complexity in advanced technology nodes, the calculation runtime of critical area has increased from hours to days and even week(s). Also FINFET brings their own challenges and new failure modes such as transistor-related defectivity and inter-layer interactions. Meanwhile, it has become more and more challenging to obtain accurate defect density by failure mode. In this paper, GlobalFoundries and Cadence describe the motivations that drove their partnership to develop a new generation of critical area analysis with adaptive sampling to reduce runtime while maintaining accuracy, especially while taking into account connectivity and transistor defectivity. After reviewing the principle and challenges of critical area calculation and yield estimation, two new methodologies of yield modeling using critical area analysis are given to address these challenges. The first methodology avoids the costly and complicated process of defect density calibration. The second methodology fulfills the wafer-based yield projection with critical area normalization and machine learning.
