This paper reviews the recent progress made at Printable Field Emitters (PFE), Ltd., in creating a 5.7-in. quarter-VGA field-emission display (FED), describing some of the technical hurdles that were overcome and quantifying the performance of the display. First, however, some detailed market analysis is presented that shows that mass-market displays in the 30-60-in.-diagonal range need to be significantly lower in cost than the present PDP technology if market penetration is to be successful. In addition, the results of cost-modeling the manufacturing of a low-cost FED with at least a printed cold-cathode layer are presented. This paper shows that by scaling-up the processes used in the demonstrator presented, sufficient cost savings are made, making a very marketable product. We present the architecture of our frit-sealed display and describe some of the testing that was performed to characterize the devices. Finally, we discuss work in progress to optimize the manufacturing route and introduce even more cost savings and performance improvements.
