Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)

التفاصيل البيبلوغرافية
العنوان: Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)
المؤلفون: Hyeongsun Hong, Hyun-Gi Kim, Hyun-Woo Chung, Chilhee Chung, Kang-Uk Kim, Yong Chul Oh, Gyo-Young Jin, Hui-jung Kim, Sua Kim, Jiyoung Kim, Yoo-Sang Hwang, Ki-whan Song
المصدر: 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).
بيانات النشر: IEEE, 2011.
سنة النشر: 2011
مصطلحات موضوعية: Materials science, business.industry, Transistor, Electrical engineering, Pillar, Subthreshold slope, law.invention, Nanoelectronics, law, Logic gate, Optoelectronics, Cell structure, Wafer, business, Dram
الوصف: New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.
URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::f259466b081869ae17b0388b3f8d6292
https://doi.org/10.1109/essderc.2011.6044197
رقم الأكسشن: edsair.doi...........f259466b081869ae17b0388b3f8d6292
قاعدة البيانات: OpenAIRE