Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels
| العنوان: | Mechanical and Electrical Analysis of Strained Liner Effect in 35 nm Fully Depleted Silicon-on-Insulator Devices with Ultra Thin Silicon Channels |
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| المؤلفون: | A. Vandooren, Francois Leverd, F. Pionnier, Sorin Cristoloveanu, Vincent Fiori, Roland Pantel, M. Broekaart, G. Imbert, Stephane Denorme, L. Gabette, Thomas Skotnicki, C. Chaton, Frederic Boeuf, F. Vigilant, S. Jullian, T. Kormann, C. Gallon, Claire Fenouillet-Beranger, Pascal Gouraud, C. Laviron, H. Bernard, Nicolas Loubet, Philippe Garnier, A. Tarnowka |
| المساهمون: | Laboratoire des technologies de la microélectronique (LTM), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Université Joseph Fourier - Grenoble 1 (UJF)-Centre National de la Recherche Scientifique (CNRS), Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS), Clot, Marielle |
| المصدر: | Japanese Journal of Applied Physics Japanese Journal of Applied Physics, Japan Society of Applied Physics, 2006, pp.Part1-45 Issue: 4B (2006) 3058-3063 Japanese Journal of Applied Physics, 2006, pp.Part1-45 Issue: 4B (2006) 3058-3063 |
| بيانات النشر: | IOP Publishing, 2006. |
| سنة النشر: | 2006 |
| مصطلحات موضوعية: | Materials science, Physics and Astronomy (miscellaneous), Silicon, General Physics and Astronomy, chemistry.chemical_element, Silicon on insulator, 02 engineering and technology, 01 natural sciences, law.invention, PMOS logic, Stress (mechanics), law, 0103 physical sciences, Ultimate tensile strength, ComputingMilieux_MISCELLANEOUS, NMOS logic, 010302 applied physics, business.industry, Transistor, General Engineering, 021001 nanoscience & nanotechnology, chemistry, Optoelectronics, Field-effect transistor, 0210 nano-technology, business |
| الوصف: | We study the effects of a strained contact etch stop layer (CESL) on fully depleted (FD) silicon-on-insulator (SOI) devices with ultra thin silicon channels. As expected from extensive simulation analysis, the electrical results demonstrate that in spite of the raised source/drain architecture, the stress is effectively transferred from the liner into the underlying channel. Using a tensile liner for the n-type metal–oxide–semiconductor field effect transistor (nMOS) and a compressive liner for the p-type metal–oxide–semiconductor field effect transistor (pMOS), transistor performance enhancements of 10% and 17%, respectively, were obtained. Moreover, with a tensile (/compressive) liner, tensile (/compressive) edge effects become dominant for short devices whereas the stress becomes less tensile (/compressive) for longer devices. Indeed, the balance between these two contributions and the strain level in the channel are highly dependent on geometrical parameters (W, Lgate). |
| تدمد: | 1347-4065 0021-4922 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a8667a54960a8a05e8ad984fd786da2b https://doi.org/10.1143/jjap.45.3058 |
| رقم الأكسشن: | edsair.doi.dedup.....a8667a54960a8a05e8ad984fd786da2b |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 13474065 00214922 |
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