We present a cryptography-oriented reconfigurable array called CryptoRA that efficiently supports very long-integer addition and subtraction. We first describe the CryptoRA architecture and show that extending the dedicated carry chains of modern FPGAs over the orthogonal direction, followed by merging two FPGA columns to create computing tiles that support both generate and propagate signals of a carry-lookahead network, provides a reduction in operation latency. Then, we show that splitting a tile's Look-Up Table into two halves provides additional benefits in terms of latency and flexibility in using the dedicated generate and propagate chains. According to our estimations, long-integer addition widely used in cryptography is more than 22% faster on CryptoRA than on Virtex-II Pro FPGA. This improvement has a large positive impact on implementing cryptography applications in embedded environments.
