Multiple Clock Domain Design
| العنوان: | Multiple Clock Domain Design |
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| المؤلفون: | Vaibbhav Taraate |
| المصدر: | Digital Logic Design Using Verilog ISBN: 9789811631986 Digital Logic Design Using Verilog ISBN: 9788132227892 |
| بيانات النشر: | Springer Singapore, 2021. |
| سنة النشر: | 2021 |
| مصطلحات موضوعية: | Computer architecture, Application-specific integrated circuit, Clock domain crossing, Clock signal, Computer science, Synchronization (computer science), Matrix clock, Verilog, Digital clock manager, computer, Domain (software engineering), computer.programming_language |
| الوصف: | In the practical ASIC and SOC designs the multiple clocks are used and the designs are called as multiple clock domain designs. These kinds of designs need to be described using the efficient design architectures and Verilog RTL. This chapter focuses in the key design techniques which are used to describe the multiple clock domain designs while passing data from one of the clock domain to other. The chapter key highlights are the detail description for the synchronizers, data path, and control path synchronization logic using the efficient Verilog RTL. This chapter also discusses on the key design challenges in the multiple clock domain designs and even this chapter focuses on the design guidelines to describe the efficient clock domain designs. |
| ردمك: | 978-81-322-2789-2 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cce9f9d114b2da6d389be8202bbf3127 https://doi.org/10.1007/978-981-16-3199-3_22 |
| حقوق: | CLOSED |
| رقم الأكسشن: | edsair.doi.dedup.....cce9f9d114b2da6d389be8202bbf3127 |
| قاعدة البيانات: | OpenAIRE |
| ردمك: | 9788132227892 |
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