The diagnosis of faults to replaceable units at the system or board level can be enhanced by selective insertion of serial scan shift registers as test points within or between the replaceable units. A systematic approach to the selection of locations for such test points in order to realize a target diagnostic resolution to the replaceable unit level is proposed. The approach is based on a combination of three models, a structural model for system interconnection and test signal propagation, a syndrome model for system diagnosability analusis, and a probabilistic model for module failure and syndrome occurrence. On the basis of these models, the average number of replaceable units which are projected to be identified as potentially faulty in a diagnosis is formulated as a single parameter diagnostic measure for a system. A test point placement algorithm is presented which makes use of this measure plus a secondary heuristic. The algorithm uses local optimization in the sense that test points are selected one at a time until the replaceable unit diagnosability target is met. The approach is particularly applicable to systems and boards using VLSI chips because of the high ratio of logic circuits to input-output pins and interchip interconnections.
