A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks
| العنوان: | A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks |
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| المؤلفون: | Heng Zhao, Sherief Reda, Hokchhay Tann |
| المصدر: | ACM Journal on Emerging Technologies in Computing Systems. 16:1-23 |
| بيانات النشر: | Association for Computing Machinery (ACM), 2019. |
| سنة النشر: | 2019 |
| مصطلحات موضوعية: | FOS: Computer and information sciences, Speedup, Computer science, Computer Vision and Pattern Recognition (cs.CV), Pipeline (computing), Iris recognition, Computer Science - Computer Vision and Pattern Recognition, 02 engineering and technology, Encoding (memory), FOS: Electrical engineering, electronic engineering, information engineering, 0202 electrical engineering, electronic engineering, information engineering, Neural and Evolutionary Computing (cs.NE), Electrical and Electronic Engineering, Field-programmable gate array, Quantization (image processing), business.industry, Deep learning, Image and Video Processing (eess.IV), Computer Science - Neural and Evolutionary Computing, Electrical Engineering and Systems Science - Image and Video Processing, 020202 computer hardware & architecture, Computer engineering, Hardware and Architecture, Hardware acceleration, 020201 artificial intelligence & image processing, Artificial intelligence, business, Software |
| الوصف: | Applications of fully convolutional networks (FCN) in iris segmentation have shown promising advances. For mobile and embedded systems, a significant challenge is that the proposed FCN architectures are extremely computationally demanding. In this article, we propose a resource-efficient, end-to-end iris recognition flow, which consists of FCN-based segmentation and a contour fitting module, followed by Daugman normalization and encoding. To attain accurate and efficient FCN models, we propose a three-step SW/HW co-design methodology consisting of FCN architectural exploration, precision quantization, and hardware acceleration. In our exploration, we propose multiple FCN models, and in comparison to previous works, our best-performing model requires 50× fewer floating-point operations per inference while achieving a new state-of-the-art segmentation accuracy. Next, we select the most efficient set of models and further reduce their computational complexity through weights and activations quantization using an 8-bit dynamic fixed-point format. Each model is then incorporated into an end-to-end flow for true recognition performance evaluation. A few of our end-to-end pipelines outperform the previous state of the art on two datasets evaluated. Finally, we propose a novel dynamic fixed-point accelerator and fully demonstrate the SW/HW co-design realization of our flow on an embedded FPGA platform. In comparison with the embedded CPU, our hardware acceleration achieves up to 8.3× speedup for the overall pipeline while using less than 15% of the available FPGA resources. We also provide comparisons between the FPGA system and an embedded GPU showing different benefits and drawbacks for the two platforms. |
| تدمد: | 1550-4840 1550-4832 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f3a0bf626c4005969d6e78656f4fa72c https://doi.org/10.1145/3357796 |
| حقوق: | OPEN |
| رقم الأكسشن: | edsair.doi.dedup.....f3a0bf626c4005969d6e78656f4fa72c |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 15504840 15504832 |
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