This thesis aims to design and implement a Post-Quantum Cryptographic (PQC) algorithm accelerator to integrate it inside a System On Chip (SoC) for FPGA and ASIC targets. The accelerated PQC algorithm is called CRYSTALS-Kyber, a key-encapsulation mechanism (KEM) belonging to public-key cryptographic schemes (PKC). This cryptosystem is selected as one of the best KEMs from the National Institute of Standards and Technology (NIST) contest. Regarding the SoC, it belongs to the DRAC project, led by the Barcelona Supercomputing Center (BSC). The objective of this project is to design and implement RISC-V processors together with accelerators to optimize applications dedicated to PQC security, personalized medicine, and autonomous navigation. As for the CRYSTALS-Kyber accelerator, it has been designed using High-Level Synthesis (HLS) description. However, two different HLS approaches had to be performed to cover FPGA and ASIC targets. For the first target (FPGA), performance results provide almost 150x of speed-up concerning specific software executions. For the second target (ASIC), the accelerator implementation achieves 1GHz in the typical corner using 22nm FD-SOI commercial technology libraries.
