تقرير
Fast inference of deep neural networks in FPGAs for particle physics
| العنوان: | Fast inference of deep neural networks in FPGAs for particle physics |
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| المؤلفون: | Duarte, Javier, Han, Song, Harris, Philip, Jindariani, Sergo, Kreinar, Edward, Kreis, Benjamin, Ngadiuba, Jennifer, Pierini, Maurizio, Rivera, Ryan, Tran, Nhan, Wu, Zhenbin |
| المصدر: | JINST 13 P07027 (2018) |
| سنة النشر: | 2018 |
| المجموعة: | Computer Science High Energy Physics - Experiment Physics (Other) Statistics |
| مصطلحات موضوعية: | Physics - Instrumentation and Detectors, Computer Science - Computer Vision and Pattern Recognition, High Energy Physics - Experiment, Statistics - Machine Learning |
| الوصف: | Recent results at the Large Hadron Collider (LHC) have pointed to enhanced physics capabilities through the improvement of the real-time event processing techniques. Machine learning methods are ubiquitous and have proven to be very powerful in LHC physics, and particle physics as a whole. However, exploration of the use of such techniques in low-latency, low-power FPGA hardware has only just begun. FPGA-based trigger and data acquisition (DAQ) systems have extremely low, sub-microsecond latency requirements that are unique to particle physics. We present a case study for neural network inference in FPGAs focusing on a classifier for jet substructure which would enable, among many other physics scenarios, searches for new dark sector particles and novel measurements of the Higgs boson. While we focus on a specific example, the lessons are far-reaching. We develop a package based on High-Level Synthesis (HLS) called hls4ml to build machine learning models in FPGAs. The use of HLS increases accessibility across a broad user community and allows for a drastic decrease in firmware development time. We map out FPGA resource usage and latency versus neural network hyperparameters to identify the problems in particle physics that would benefit from performing neural network inference with FPGAs. For our example jet substructure model, we fit well within the available resources of modern FPGAs with a latency on the scale of 100 ns. Comment: 22 pages, 17 figures, 2 tables, JINST revision |
| نوع الوثيقة: | Working Paper |
| DOI: | 10.1088/1748-0221/13/07/P07027 |
| URL الوصول: | http://arxiv.org/abs/1804.06913 |
| رقم الأكسشن: | edsarx.1804.06913 |
| قاعدة البيانات: | arXiv |
| DOI: | 10.1088/1748-0221/13/07/P07027 |
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