تقرير
Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices
| العنوان: | Evaluation of Single-Chip, Real-Time Tomographic Data Processing on FPGA - SoC Devices |
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| المؤلفون: | Korcyl, G., Białas, P., Curceanu, C., Czerwiński, E., Dulski, K., Flak, B., Gajos, A., Głowacz, B., Gorgol, M., Hiesmayr, B. C., Jasińska, B., Kacprzak, K., Kajetanowicz, M., Kisielewska, D., Kowalski, P., Kozik, T., Krawczyk, N., Krzemień, W., Kubicz, E., Mohammed, M., Niedźwiecki, Sz., Pawlik-Niedźwiecka, M., Pałka, M., Raczyński, L., Rajda, P., Rudy, Z., Salabura, P., Sharma, N. G., Sharma, S., Shopa, R. Y., Skurzok, M., Silarski, M., Strzempek, P., Wieczorek, A., Wiślicki, W., Zaleski, R., Zgardzińska, B., Zieliński, M., Moskal, P. |
| سنة النشر: | 2018 |
| المجموعة: | Physics (Other) |
| مصطلحات موضوعية: | Physics - Instrumentation and Detectors |
| الوصف: | A novel approach to tomographic data processing has been developed and evaluated using the Jagiellonian PET (J-PET) scanner as an example. We propose a system in which there is no need for powerful, local to the scanner processing facility, capable to reconstruct images on the fly. Instead we introduce a Field Programmable Gate Array (FPGA) System-on-Chip (SoC) platform connected directly to data streams coming from the scanner, which can perform event building, filtering, coincidence search and Region-Of-Response (ROR) reconstruction by the programmable logic and visualization by the integrated processors. The platform significantly reduces data volume converting raw data to a list-mode representation, while generating visualization on the fly. Comment: IEEE Transactions on Medical Imaging, 17 May 2018 |
| نوع الوثيقة: | Working Paper |
| DOI: | 10.1109/TMI.2018.2837741 |
| URL الوصول: | http://arxiv.org/abs/1807.10754 |
| رقم الأكسشن: | edsarx.1807.10754 |
| قاعدة البيانات: | arXiv |
| DOI: | 10.1109/TMI.2018.2837741 |
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