تقرير
A Classical Architecture For Digital Quantum Computers
| العنوان: | A Classical Architecture For Digital Quantum Computers |
|---|---|
| المؤلفون: | Zhang, Fang, Zhu, Xing, Chao, Rui, Huang, Cupjin, Kong, Linghang, Chen, Guoyang, Ding, Dawei, Feng, Haishan, Gao, Yihuai, Ni, Xiaotong, Qiu, Liwei, Wei, Zhe, Yang, Yueming, Zhao, Yang, Shi, Yaoyun, Zhang, Weifeng, Zhou, Peng, Chen, Jianxin |
| سنة النشر: | 2023 |
| المجموعة: | Computer Science Quantum Physics |
| مصطلحات موضوعية: | Quantum Physics, Computer Science - Hardware Architecture |
| الوصف: | Scaling bottlenecks the making of digital quantum computers, posing challenges from both the quantum and the classical components. We present a classical architecture to cope with a comprehensive list of the latter challenges {\em all at once}, and implement it fully in an end-to-end system by integrating a multi-core RISC-V CPU with our in-house control electronics. Our architecture enables scalable, high-precision control of large quantum processors and accommodates evolving requirements of quantum hardware. A central feature is a microarchitecture executing quantum operations in parallel on arbitrary predefined qubit groups. Another key feature is a reconfigurable quantum instruction set that supports easy qubit re-grouping and instructions extensions. As a demonstration, we implement the widely-studied surface code quantum computing workflow, which is instructive for being demanding on both the controllers and the integrated classical computation. Our design, for the first time, reduces instruction issuing and transmission costs to constants, which do not scale with the number of qubits, without adding any overheads in decoding or dispatching. Rather than relying on specialized hardware for syndrome decoding, our system uses a dedicated multi-core CPU for both qubit control and classical computation, including syndrome decoding. This simplifies the system design and facilitates load-balancing between the quantum and classical components. We implement recent proposals as decoding firmware on a RISC-V system-on-chip (SoC) that parallelizes general inner decoders. By using our in-house Union-Find and PyMatching 2 implementations, we can achieve unprecedented decoding capabilities of up to distances 47 and 67 with the currently available SoCs, under realistic and optimistic assumptions of physical error rate $p=0.001 and p=0.0001, respectively, all in just 1 \textmu s. Comment: 12 pages, 12 figures |
| نوع الوثيقة: | Working Paper |
| URL الوصول: | http://arxiv.org/abs/2305.14304 |
| رقم الأكسشن: | edsarx.2305.14304 |
| قاعدة البيانات: | arXiv |
| الوصف غير متاح. |