تقرير
Cryogenic Reconfigurable Logic with Superconducting Heater Cryotron: Enhancing Area Efficiency and Enabling Camouflaged Processors
| العنوان: | Cryogenic Reconfigurable Logic with Superconducting Heater Cryotron: Enhancing Area Efficiency and Enabling Camouflaged Processors |
|---|---|
| المؤلفون: | Alam, Shamiul, Rampini, Dana S., Oripov, Bakhrom G., McCaughan, Adam N., Aziz, Ahmedullah |
| سنة النشر: | 2023 |
| المجموعة: | Computer Science Condensed Matter Physics (Other) |
| مصطلحات موضوعية: | Computer Science - Emerging Technologies, Condensed Matter - Superconductivity, Computer Science - Hardware Architecture, Physics - Applied Physics |
| الوصف: | Superconducting electronics are among the most promising alternatives to conventional CMOS technology thanks to the ultra-fast speed and ultra-high energy efficiency of the superconducting devices. Having a cryogenic control processor is also a crucial requirement for scaling the existing quantum computers up to thousands of qubits. Despite showing outstanding speed and energy efficiency, Josephson junction-based circuits suffer from several challenges such as flux trapping leading to limited scalability, difficulty in driving high impedances, and so on. Three-terminal cryotron devices have been proposed to solve these issues which can drive high impedances (>100 k{\Omega}) and are free from any flux trapping issue. In this work, we develop a reconfigurable logic circuit using a heater cryotron (hTron). In conventional approaches, the number of devices to perform a logic operation typically increases with the number of inputs. However, here, we demonstrate a single hTron device-based logic circuit that can be reconfigured to perform 1-input copy and NOT, 2-input AND and OR, and 3-input majority logic operations by choosing suitable biasing conditions. Consequently, we can perform any processing task with a much smaller number of devices. Also, since we can perform different logic operations with the same circuit (same layout), we can develop a camouflaged system where all the logic gates will have the same layout. Therefore, this proposed circuit will ensure enhanced hardware security against reverse engineering attacks. Comment: 13 pages, 6 figures |
| نوع الوثيقة: | Working Paper |
| URL الوصول: | http://arxiv.org/abs/2306.10244 |
| رقم الأكسشن: | edsarx.2306.10244 |
| قاعدة البيانات: | arXiv |
| الوصف غير متاح. |