تقرير
An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators
| العنوان: | An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators |
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| المؤلفون: | Ferry, Corentin, Derumigny, Nicolas, Derrien, Steven, Rajopadhye, Sanjay |
| سنة النشر: | 2024 |
| المجموعة: | Computer Science |
| مصطلحات موضوعية: | Computer Science - Hardware Architecture |
| الوصف: | Memory bandwidth is known to be a performance bottleneck for FPGA accelerators, especially when they deal with large multi-dimensional data-sets. A large body of work focuses on reducing of off-chip transfers, but few authors try to improve the efficiency of transfers. This paper addresses the later issue by proposing (i) a compiler-based approach to accelerator's data layout to maximize contiguous access to off-chip memory, and (ii) data packing and runtime compression techniques that take advantage of this layout to further improve memory performance. We show that our approach can decrease the I/O cycles up to $7\times$ compared to un-optimized memory accesses. Comment: 11 pages, 11 figures, 2 tables |
| نوع الوثيقة: | Working Paper |
| URL الوصول: | http://arxiv.org/abs/2401.12071 |
| رقم الأكسشن: | edsarx.2401.12071 |
| قاعدة البيانات: | arXiv |
| الوصف غير متاح. |