This paper presents a novel power efficient Hybrid floating point multiplier (HFPM) with approximate hybrid radix-4/radix-8 booth encoder. This approach efficiently increases the speed of operation and optimises hardware. Compared to existing HFPMs, the proposed HFPM utilises a novel hybrid radix-4/radix-8 booth encoder. The hybrid architecture reduces the computations by an average of k/3 for a k-bit 2’s complement representation by reducing the number of partial products. In addition, to achieve an area-efficient and power-efficient design, approximate computational units are added to the radix-8 booth encoder in the hybrid architecture with a slight reduction in accuracy. The efficiency of the approximate architecture is measured in scales of Error Rate (ER) and Normalized Error Distance (NED). The proposed design is implemented on Kintex 7 FPGA and realized on 45nm ASIC platforms. The experimental study shows that the proposed multiplier has utilised hardware (831 slice LUT, 828 LUT as logic) and consumed 6110 μm2 of area and 83 μW of power which is less as compared to existing floating point multipliers. The experimental results in terms of average Structural Similarity Index Measure (SSIM) is 0.98 which is better than the existing floating point multipliers are compared.
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