Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size

التفاصيل البيبلوغرافية
العنوان:	Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size
المؤلفون:	Yu, X.-R., Chuang, M.-H., Chang, S.-W., Chang, W.-H., Hong, T.-C., Chiang, C.-H., Lu, W.-H., Yang, C.-Y., Chen, W.-J., Lin, J.-H., Wu, P.-H., Sun, T.-C., Kola, S., Yang, Y.-S., Da, Yun, Sung, P.-J., Wu, C.-T., Cho, T.-C., Luo, G.-L., Kao, K.-H., Chiang, M.-H., Ma, W. C.-Y., Su, C.-J., Chao, T.-S., Maeda, T., Samukawa, S., Li, Y., Lee, Y.-J., Wu, W.-F., Tarng, J.-H., Wang, Y.-H.
المصدر:	2022 International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2022 International. :20.5.1-20.5.4 Dec, 2022
Relation:	2022 IEEE International Electron Devices Meeting (IEDM)
قاعدة البيانات:	IEEE Xplore Digital Library