دورية أكاديمية
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique
| العنوان: | A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique |
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| المؤلفون: | Wang, L., Chen, Y., Yang, C., Zhao, X., Mak, P., Maloberti, F., Martins, R.P. |
| المصدر: | IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 70(7):2637-2650 Jul, 2023 |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | تدمد: | 15498328 15580806 |
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| DOI: | 10.1109/TCSI.2023.3263963 |