مؤتمر
A Synthesis Method for Verilog Case Statement Using Mux-and-Inverter Graph
| العنوان: | A Synthesis Method for Verilog Case Statement Using Mux-and-Inverter Graph |
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| المؤلفون: | Wang, Zhuoli, Chen, Lei, Wang, Shuo, Zhou, Jing, Tian, Chunsheng, Feng, Hanxu |
| المصدر: | 2023 International Symposium of Electronics Design Automation (ISEDA) Electronics Design Automation (ISEDA), 2023 International Symposium of. :174-178 May, 2023 |
| Relation: | 2023 International Symposium of Electronics Design Automation (ISEDA) |
| قاعدة البيانات: | IEEE Xplore Digital Library |
| ردمك: | 9798350304510 9798350304503 |
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| DOI: | 10.1109/ISEDA59274.2023.10218672 |