مؤتمر
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis
| العنوان: | Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis |
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| المؤلفون: | Ammes, Gabriel, Butzen, Paulo F., Reis, Andre I., Ribas, Renato P. |
| المصدر: | 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) VLSI (ISVLSI), 2023 IEEE Computer Society Annual Symposium on. :1-6 Jun, 2023 |
| Relation: | 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 9798350327694 |
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| تدمد: | 21593477 |
| DOI: | 10.1109/ISVLSI59464.2023.10238642 |