A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency

التفاصيل البيبلوغرافية
العنوان: A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency
المؤلفون: Tang, Tianwen, Liscidini, Antonio
المصدر: ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC) Solid State Circuits Conference (ESSCIRC), ESSCIRC 2023- IEEE 49th European. :473-476 Sep, 2023
Relation: ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:9798350304206
9798350304190
تدمد:26431319
DOI:10.1109/ESSCIRC59616.2023.10268776