التفاصيل البيبلوغرافية
| العنوان: |
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS |
| المؤلفون: |
Wang, Zhongkai, Choi, Minsoo, Kwon, Paul, Liu, Zhaokai, Yin, Bozhi, Lee, Kyoungtae, Park, Kwanseo, Biswas, Ayan, Han, Jaeduk, Du, Sijun, Alon, Elad |
| المصدر: |
2024 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2024 IEEE International Symposium on. :1-5 May, 2024 |
| Relation: |
2024 IEEE International Symposium on Circuits and Systems (ISCAS) |
| قاعدة البيانات: |
IEEE Xplore Digital Library |
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