مؤتمر
Clock network analysis at the pre-layout stage for efficient clock tree synthesis [SOC design]
| العنوان: | Clock network analysis at the pre-layout stage for efficient clock tree synthesis [SOC design] |
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| المؤلفون: | Myung-soo Jang, Joo-Hyun Park, Young-Nam Yeon, Jin-Yong Lee, Kyu-Myung Choi, Jeong-Taek Kong |
| المصدر: | 15th Annual IEEE International ASIC/SOC Conference ASIC/SOC conference ASIC/SOC Conference, 2002. 15th Annual IEEE International. :363-367 2002 |
| Relation: | Proceedings 15th Annual IEEE International ASIC/SOC Conference |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 0780374940 9780780374942 |
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| DOI: | 10.1109/ASIC.2002.1158086 |