Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

التفاصيل البيبلوغرافية
العنوان: Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
المؤلفون: Yang, H.S., Malik, R., Narasimha, S., Li, Y., Divakaruni, R., Agnello, P., Allen, S., Antreasyan, A., Arnold, J.C., Bandy, K., Belyansky, M., Bonnoit, A., Bronner, G., Chan, V., Chen, X., Chen, Z., Chidambarrao, D., Chou, A., Clark, W., Crowder, S.W., Engel, B., Harifuchi, H., Huang, S.F., Jagannathan, R., Jamin, F.F., Kohyama, Y., Kuroda, H., Lai, C.W., Lee, H.K., Lee, W.-H., Lim, E.H., Lai, W., Mallikarjunan, A., Matsumoto, K., McKnight, A., Nayak, J., Ng, H.Y., Panda, S., Rengarajan, R., Steigerwalt, M., Subbanna, S., Subramanian, K., Sudijono, J., Sudo, G., Sun, S.-P., Tessier, B., Toyoshima, Y., Tran, P., Wise, R., Wong, R., Yang, I.Y., Wann, C.H., Su, L.T., Horstmann, M., Feudel, Th., Wei, A., Frohberg, K., Burbach, G., Gerhardt, M., Lenski, M., Stephan, R., Wieczorek, K., Schaller, M., Salz, H., Hohage, J., Ruelke, H., Klais, J., Huebler, P., Luning, S., van Bentum, R., Grasshoff, G., Schwan, C., Ehrichs, E., Goad, S., Buller, J., Krishnan, S., Greenlaw, D., Raab, M., Kepler, N.
المصدر: IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. Electron devices meeting Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. :1075-1077 2004
Relation: 2004 International Electron Devices Meeting
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:0780386841
9780780386846
DOI:10.1109/IEDM.2004.1419385