Yield enhancement through fast statistical scan test analysis for digital logic

التفاصيل البيبلوغرافية
العنوان: Yield enhancement through fast statistical scan test analysis for digital logic
المؤلفون: Erb, H., Burmer, C., Leininger, A.
المصدر: IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005. Advanced Semiconductor Manufacturing Conference and Workshop, 2005 IEEE/SEMI. :250-255 2005
Relation: IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005.
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:0780389972
9780780389977
تدمد:10788743
23766697
DOI:10.1109/ASMC.2005.1438804