A linear model for high-level delay estimation in VDSM on-chip interconnects

التفاصيل البيبلوغرافية
العنوان: A linear model for high-level delay estimation in VDSM on-chip interconnects
المؤلفون: Murgan, T., Ortiz, A.G., Petrov, M., Glesner, M.
المصدر: 2005 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and systems Circuits and Systems (ISCAS), 2005 IEEE International Symposium on. :1078-1081 Vol. 2 2005
Relation: 2005 IEEE International Symposium on Circuits and Systems (ISCAS)
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:0780388348
9780780388345
تدمد:02714302
21581525
DOI:10.1109/ISCAS.2005.1464779