مؤتمر
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
| العنوان: | Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint |
|---|---|
| المؤلفون: | Pandey, S., Glesner, M. |
| المصدر: | 2006 43rd ACM/IEEE Design Automation Conference Design Automation Conference Design Automation Conference, 2006 43rd ACM/IEEE. :663-668 2006 |
| Relation: | 2006 Design Automation Conference |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 1595933816 9781595933812 |
|---|---|
| تدمد: | 0738100X |
| DOI: | 10.1145/1146909.1147078 |