An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme

التفاصيل البيبلوغرافية
العنوان: An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme
المؤلفون: Kyu-hyoun Kim, Uksong Kang, Hoe-Ju Chung, Duk-Ha Park, Woo-Seop Kim, Young-Chan Jang, Moonsook Park, Hoon Lee, Jin-Young Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo Sun Choi, Changhyun Kim
المصدر: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International. :527-536 2006
Relation: 2006 IEEE International Solid State Circuits Conference
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:1424400791
9781424400799
تدمد:01936530
23768606
DOI:10.1109/ISSCC.2006.1696089