مؤتمر
Flexible timing specification in a VHDL synthesis subset
| العنوان: | Flexible timing specification in a VHDL synthesis subset |
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| المؤلفون: | Stoll, A., Biesenack, J., Rumler, S. |
| المصدر: | Proceedings EURO-DAC '92: European Design Automation Conference Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European. :610-615 1992 |
| Relation: | Proceedings EURO-DAC '92: European Design Automation Conference |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 0818627808 9780818627804 |
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| DOI: | 10.1109/EURDAC.1992.246334 |