A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

التفاصيل البيبلوغرافية
العنوان:	A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process
المؤلفون:	Chen, X., Samavedam, S., Narayanan, V., Stein, K., Hobbs, C., Baiocco, C., Li, W., Jaeger, D., Zaleski, M., Yang, H. S., Kim, N., Lee, Y., Zhang, D., Kang, L., Chen, J., Zhuang, H., Sheikh, A., Wallner, J., Aquilino, M., Han, J., Jin, Z., Li, J., Massey, G., Kalpat, S., Jha, R., Moumen, N., Mo, R., Kirshnan, S., Wang, X., Chudzik, M., Chowdhury, M., Nair, D., Reddy, C., Teh, Y. W., Kothandaraman, C., Coolbaugh, D., Pandey, S., Tekleab, D., Thean, A., Sherony, M., Lage, C., Sudijono, J., Lindsay, R., Ku, J. H., Khare, M., Steegen, A.
المصدر:	2008 Symposium on VLSI Technology VLSI Technology, 2008 Symposium on. :88-89 Jun, 2008
Relation:	2008 Symposium on VLSI Technology
قاعدة البيانات:	IEEE Xplore Digital Library