التفاصيل البيبلوغرافية
| العنوان: |
High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper |
| المؤلفون: |
Greene, B., Liang, Q., Amarnath, K., Wang, Y., Schaeffer, J., Cai, M., Liang, Y., Saroop, S., Cheng, J., Rotondaro, A., Han, S.-J., Mo, R., McStay, K., Ku, S., Pal, R., Kumar, M., Dirahoui, B., Yang, B., Tamweber, F., Lee, W.-H., Steigerwalt, M., Weijtmans, H., Holt, J., Black, L., Samavedam, S., Turner, M., Ramani, K., Lee, D., Belyansky, M., Chowdhury, M., Aime, D., Min, B., van Meer, H., Yin, H., Chan, K., Angyal, M., Zaleski, M., Ogunsola, O., Child, C., Zhuang, L., Yan, H., Permanaa, D., Sleight, J., Guo, D., Mittl, S., Ioannou, D., Wu, E., Chudzik, M., Park, D.-G., Brown, D., Luning, S., Mocuta, D., Maciejewski, E., Henson, K., Leobandung, E. |
| المصدر: |
2009 Symposium on VLSI Technology VLSI Technology, 2009 Symposium on. :140-141 Jun, 2009 |
| Relation: |
2009 Symposium on VLSI Technology |
| قاعدة البيانات: |
IEEE Xplore Digital Library |
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