دورية أكاديمية
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique
| العنوان: | A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique |
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| المؤلفون: | Cho, Y.-K., Jeon, Y.-D., Nam, J.-W., Kwon, J.-K. |
| المصدر: | IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 57(7):502-506 Jul, 2010 |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | تدمد: | 15497747 15583791 |
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| DOI: | 10.1109/TCSII.2010.2048387 |