مؤتمر
A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM
| العنوان: | A built-in self-test circuit with timing margin test function in a 1 Gbit synchronous DRAM |
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| المؤلفون: | Sakashita, N., Okuda, F., Shimomura, K., Shimano, H., Hamada, M., Tada, T., Komori, S., Kyuma, K., Yasuoka, A., Abe, H. |
| المصدر: | Proceedings International Test Conference 1996. Test and Design Validity International test conference Test Conference, 1996. Proceedings., International. :319-324 1996 |
| Relation: | Proceedings International Test Conference 1996. Test and Design Validity |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 0780335414 9780780335417 |
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| تدمد: | 10893539 |
| DOI: | 10.1109/TEST.1996.556977 |