مؤتمر
A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS
| العنوان: | A performance study of layout and Vt options for low noise amplifier design in 65-nm CMOS |
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| المؤلفون: | Pan, Quan, Yeh, Tzu-Jin, Jou, Chewnpu, Hsueh, Fu-Lung, Luong, Howard, Yue, C. Patrick |
| المصدر: | 2012 IEEE Radio Frequency Integrated Circuits Symposium Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE. :535-538 Jun, 2012 |
| Relation: | 2012 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 9781467304153 9781467304139 9781467304160 |
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| تدمد: | 15292517 23750995 |
| DOI: | 10.1109/RFIC.2012.6242340 |