Device and process optimization for a low voltage enhancement mode power heterojunction FET for portable applications

التفاصيل البيبلوغرافية
العنوان: Device and process optimization for a low voltage enhancement mode power heterojunction FET for portable applications
المؤلفون: Huang, J.H., Glass, E., Abrokwah, J., Bernhardt, B., Majerus, M., Spears, E., Parsey, J.M., Jr., Scheitlin, D., Droopad, R., Mills, L.A., Hawthorne, K., Blaugh, J.
المصدر: GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997 GaAs IC symposium Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1997. Technical Digest 1997., 19th Annual. :55-58 1997
Relation: GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:0780340833
9780780340831
تدمد:10647775
DOI:10.1109/GAAS.1997.628236