دورية أكاديمية
Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering
| العنوان: | Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering |
|---|---|
| المؤلفون: | Huang, Y.-C., Tsai, M.-H., Ding, W.-S., Li, J. C.-M., Chang, M.-T., Tseng, C.-M., Li, H.-C. |
| المصدر: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 32(4):644-652 Apr, 2013 |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | تدمد: | 02780070 19374151 |
|---|---|
| DOI: | 10.1109/TCAD.2012.2228741 |