Wafer-Level Transmission Line Pulse Testing for Optimization of Output Transistor ESD Resistance

التفاصيل البيبلوغرافية
العنوان: Wafer-Level Transmission Line Pulse Testing for Optimization of Output Transistor ESD Resistance
المؤلفون: Miller, J.W., Dickson, N., Rushing, T.
المصدر: International Integrated Reliability Workshop Final Report Integrated Reliability Workshop Final Report, 1993 International. :208-214 1993
Relation: International Integrated Reliability Workshop Final Report
قاعدة البيانات: IEEE Xplore Digital Library