A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

التفاصيل البيبلوغرافية
العنوان: A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement
المؤلفون: Nakata, Yohei, Kimi, Yuta, Okumura, Shunsuke, Jung, Jinwook, Sawada, Takuya, Toshikawa, Taku, Nagata, Makoto, Nakano, Hirofumi, Yabuuchi, Makoto, Fujiwara, Hidehiro, Nii, Koji, Kawai, Hiroyuki, Kawaguchi, Hiroshi, Yoshimoto, Masahiko
المصدر: Fifteenth International Symposium on Quality Electronic Design Quality Electronic Design (ISQED), 2014 15th International Symposium on. :16-23 Mar, 2014
Relation: 2014 15th International Symposium on Quality Electronic Design (ISQED)
قاعدة البيانات: IEEE Xplore Digital Library