مؤتمر
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS
| العنوان: | A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS |
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| المؤلفون: | Elshazly, Amr, Balankutty, Ajay, Yan-Yu Huang, Kai Yu, O'Mahony, Frank |
| المصدر: | 2014 Symposium on VLSI Circuits Digest of Technical Papers VLSI Circuits Digest of Technical Papers, 2014 Symposium on. :1-2 Jun, 2014 |
| Relation: | 2014 IEEE Symposium on VLSI Circuits |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 9781479933273 9781479933266 9781479933280 |
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| تدمد: | 21585601 21585636 |
| DOI: | 10.1109/VLSIC.2014.6858375 |