مؤتمر
Formal verification of VHDL: the model checker CV
| العنوان: | Formal verification of VHDL: the model checker CV |
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| المؤلفون: | Deharbe, D., Shankar, S., Clarke, E.M. |
| المصدر: | Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216) Integrated circuit design Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on. :95-98 1998 |
| Relation: | Proceedings. XI Brazilian Symposium on Integrated Circuit Design (Cat. No.98EX216) |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 0818687045 9780818687044 |
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| DOI: | 10.1109/SBCCI.1998.715418 |