دورية أكاديمية
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
| العنوان: | Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication |
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| المؤلفون: | Gorgin, S., Jaberipur, G. |
| المصدر: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 25(1):75-86 Jan, 2017 |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | تدمد: | 10638210 15579999 |
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| DOI: | 10.1109/TVLSI.2016.2579667 |